Case Study: Comparison between Conventional VHDL and UVM Test-Benches for a Slave IS Transceiver

In this survey, we prove that the Universal Verification Methodology, UVM, is not only efficient in verifying large-gate-count IP-based System-on-Chip designs, but it is also efficient in verifying small designs, in comparison with the conventional verification techniques, specifically VHDL testbenches. We have built both a UVM verification environment and a VHDL test-bench to verify the operation of an IS slave transceiver, which is a relatively small design in terms of gate count. It utilizes 197 LUTs on Xilinx Spartan 6 FPGA. We provide a comparison between the two approaches in both the development and runtime phases. Index Terms – Functional verification, UVM, IS, VHDL, test-